A solution of heterogenous 3D integration of integrated circuits
The printed interposer

Background

With the increasing importance of mobile electronics, the form factor is increasingly important. This leads to more and more functions and chips being integrated into even smaller volumes.

This mega trend means that the electronic components are no longer contiguous but are arranged in stacks. This presents a particular challenge due to the fact that the stacked components have different geometric dimensions and their contact surfaces are also very different. The currently used technology of Si interposers can meet these requirements but is very limited in flexibility and cost.

 

Solution

DA method of printing of functional structures applied directly to a wiring layer on the surface of a device that allows electrical contact to the next component. The connections between the chips to be stacked is printed on the finished wafer or on the individual component (chip) in the form a multilayered sequence. The first layer, created using screen printing or direct printing with Aerosol-Jet or Inkjet technics, is an insulation layer that is cured by UV light with the required contact areas left open. The open contact surfaces are then filled with a metallic ink, using an aerosol jet printing process, filled and cured with the help of a laser, and then the conductors are printed for the connections to the chips allowing them to be stacked. Finally, another insulating layer is applied with open contact surfaces at the required connection points, which later fulfill the function of the normal metal bonding bumps. In addition, between the printing of the insulating and conductive materials, several more conductive and insulating layers can also be generated which allow the conductors to be crossed.

A printed interposer is much more flexible and easier to produce than the currently used Si interposer. It can also be used for applications that were not previously possible with the existing technologies. In smaller production volumes, it is significantly less costly and requires much less resource in terms of machines, materials, energy and manpower.

Picture 1:
Picture 1
Si-Interposer with TSV-Process as 3D-Stack

 

Picture 2:Picture 2
From wafer to 3D IC via printed interposer

 

Picture 3:Picture 3
The printing: yellow areas = nonconductive areas / orange areas = conductive paths with red areas = contact points (Bumps)